Method of Manufacturing an Integrated Circuit

ABSTRACT

A method of manufacturing an integrated circuit includes: growing an epitaxial layer on a process surface of a base substrate; forming, by processes applied to an exposed first surface of the epitaxial layer, first transistor cells in the epitaxial layer, each first transistor cell including a first gate electrode; and forming, by processes applied to a surface opposite to the first surface, second transistor cells, each second transistor cell including a second gate electrode.

BACKGROUND

Integrated circuits may integrate several switching devices. Forexample, integrated half bridge circuits combine high side and low sideswitches arranged side-by-side in the same semiconductor die. There is aneed for improved power switching devices.

SUMMARY

According to an embodiment, an integrated circuit includes a firstswitching device including a first semiconductor region in a firstsection of a semiconductor portion and a second switching deviceincluding a second semiconductor region in a second section of thesemiconductor portion. The first and second sections as well aselectrode structures of the first and second switching devices outsidethe semiconductor portion are arranged along a vertical axisperpendicular to a first surface of the semiconductor portion.

Another embodiment refers to a method of manufacturing a semiconductordevice. An epitaxial layer grows on a process surface of a basesubstrate. Processes applied to an exposed first surface of theepitaxial layer provide first transistor cells in the epitaxial layer,wherein each first transistor cell includes a first gate electrode.Processes applied to a surface opposite to the first surface providesecond transistor cells, wherein each second transistor cell includes asecond gate electrode.

Those skilled in the art will recognize additional features andadvantages upon reading the following detailed description and onviewing the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the invention and are incorporated in and constitute apart of this specification. The drawings illustrate the embodiments ofthe present invention and together with the description serve to explainprinciples of the invention. Other embodiments of the invention andintended advantages will be readily appreciated as they become betterunderstood by reference to the following detailed description.

FIG. 1A is a schematic circuit diagram of an integrated circuitincluding a half bridge circuit with the low and high side switchesembodied as n-FETs (n channel field effect transistors).

FIG. 1B is a schematic cross-sectional view of a portion of theintegrated circuit of FIG. 1A in accordance with an embodiment providinga lateral n-FET as high side switch and a vertical n-FET as low sideswitch.

FIG. 1C is a schematic cross-sectional view of a portion of theintegrated circuit of FIG. 1A according to an embodiment providing alateral n-FET as high side switch and a vertical n-FET as low sideswitch as well as a laterally patterned body connection for the highside switch.

FIG. 1D is a schematic plan view of a first side of the integratedcircuit of FIG. 1A according to an embodiment.

FIG. 1E is a schematic plan view of a second side of the integratedcircuit of FIG. 1A according to an embodiment.

FIG. 2A is a schematic circuit diagram of an integrated circuitincluding a half bridge circuit with a p-FET high side switch and ann-FET low side switch.

FIG. 2B is a schematic cross-sectional view of a portion of theintegrated circuit of FIG. 2A in accordance with an embodiment providinga lateral p-FET as high side switch and a vertical n-FET as low sideswitch.

FIG. 3A is a schematic circuit diagram of an integrated circuitaccording to an embodiment including an HEMT (high electron mobilitytransistor) and an n-FET in a cascode configuration.

FIG. 3B is a schematic cross-sectional view of a portion of theintegrated circuit of FIG. 3A in accordance with an embodiment providinga vertical n-FET.

FIG. 4A is a schematic circuit diagram of an integrated circuitincluding two HEMTs electrically arranged in series.

FIG. 4B is a schematic cross-sectional view of a portion of theintegrated circuit of FIG. 4A.

FIG. 5A is a schematic cross-sectional view of a portion of asemiconductor substrate in an exemplary method of manufacturing asemiconductor device including vertically integrated switching devicesafter providing an auxiliary structure on a first process surface of abase substrate.

FIG. 5B is a schematic cross-sectional view of the semiconductorsubstrate portion of FIG. 5A after growing a first epitaxial layer onthe base substrate.

FIG. 5C is a schematic cross-sectional view of the semiconductorsubstrate portion of FIG. 5B after providing first provisionaltransistor cells in the first epitaxial layer.

FIG. 5D is a schematic cross-sectional view of the semiconductorsubstrate portion of FIG. 5C after applying a carrier on the side of thefirst epitaxial layer.

FIG. 5E is a schematic cross-sectional view of the semiconductorsubstrate portion of FIG. 5D after flipping the semiconductor substrateand removing the base substrate.

FIG. 5F is a schematic cross-sectional view of the semiconductorsubstrate portion of FIG. 5E after providing second provisionaltransistor cells.

FIG. 5G is a schematic cross-sectional view of the semiconductorsubstrate portion of FIG. 5F after forming device connection structures.

FIG. 6A is a schematic cross-sectional view of a portion of asemiconductor substrate in an exemplary method of manufacturing anintegrated circuit by providing vertically integrated HEMTs aftergrowing a first epitaxial layer on a first process surface of a basesubstrate.

FIG. 6B is a schematic cross-sectional view of the semiconductorsubstrate portion of FIG. 6A after providing first transistor cells onand in the first epitaxial layer.

FIG. 6C is a schematic cross-sectional view of the semiconductorsubstrate portion of FIG. 6B after flipping the semiconductor substrateand thinning the base substrate.

FIG. 6D is a schematic cross-sectional view of the semiconductorsubstrate portion of FIG. 6C after growing a second epitaxial layer onthe thinned base substrate on a side opposite to the first processsurface.

FIG. 6E is a schematic cross-sectional view of the semiconductorsubstrate portion of FIG. 6D after providing second transistor cells onand in the second epitaxial layer.

DETAILED DESCRIPTION

In the following detailed description, reference is made to theaccompanying drawings, which form a part hereof, and in which are shownby way of illustrations specific embodiments in which the invention maybe practiced. Other embodiments may be utilized and structural orlogical changes may be made without departing from the scope of thepresent invention. For example, features illustrated or described forone embodiment can be used on or in conjunction with other embodimentsto yield yet a further embodiment. It is intended that the presentinvention includes such modifications and variations. The examples aredescribed using specific language that should not be construed aslimiting the scope of the appending claims. The drawings are not scaledand are for illustrative purposes only. For clarity, the same elementshave been designated by corresponding references in the differentdrawings if not stated otherwise.

The terms “having,” “containing,” “including,” “comprising” and the likeare open and the terms indicate the presence of stated structures,elements or features but not preclude additional elements or features.The articles “a,” “an” and “the” are intended to include the plural aswell as the singular, unless the context clearly indicates otherwise.

The term “electrically connected” describes a permanent low-ohmicconnection between electrically connected elements, for example a directcontact between the concerned elements or a low-ohmic connection via ametal and/or highly doped semiconductor. The term “electrically coupled”includes that one or more intervening element(s) adapted for signaltransmission may be provided between the electrically coupled elements,for example elements that are controllable to temporarily provide alow-ohmic connection in a first state and a high-ohmic electricdecoupling in a second state.

The Figures illustrate relative doping concentrations by indicating “−”or “+” next to the doping type “n” or “p.” For example, “n” means adoping concentration that is lower than the doping concentration of an“n”-doping region while an “n⁺”-doping region has a higher dopingconcentration than an “n”-doping region. Doping regions of the samerelative doping concentration do not necessarily have the same absolutedoping concentration. For example, two different “n”-doping regions mayhave the same or different absolute doping concentrations.

The embodiments relate to integrated circuits vertically integrating atleast a first and a second switching device T1, T2. Apart from the firstand second switching devices T1, T2 the integrated circuits may includefurther switching devices, electronic circuits and/or semiconductorelements. Exemplary switching devices T1, T2 include a p-FET (p channelfield effect transistor) of the depletion or enhancement mode, an n-FETof the depletion or enhancement mode, an HEMT or a JFET (junction fieldeffect transistor).

With respect to two parallel main surfaces along which electrodestructures of the first and second switching devices T1, T2 provideelectric access to the switching devices T1, T2, each of the switchingdevices T1, T2 may be a lateral switching device or a vertical switchingdevice, wherein in lateral switching devices a load current flowsparallel to the main surfaces and wherein in vertical devices the loadcurrent flows in a vertical direction perpendicular to the mainsurfaces.

The load paths of the first and second switching devices T1, T2 may beelectrically arranged in series, for example with two electricallyconnected control inputs or two separate control inputs, e.g. in acascode configuration, or may be electrically arranged in parallel, forexample with two separate or two electrically connected control inputs.

The embodiments of FIGS. 1A to 1E refer to an integrated circuitincluding n-FETs with load paths electrically arranged in series andusable, for example, as a half bridge circuit.

According to FIG. 1A, the first and second switching devices T1, T2 ofan integrated circuit 500 may be FETs, e.g. Power MOSFETs, with the loadpaths between drain D and source S connected in series between a firstload terminal Vdd and a second load terminal Gnd of the integratedcircuit 500. The drain D of the first switching device T1 may beelectrically connected or coupled to the first load terminal Vdd. Thesource S of the second switching device T2 may be electrically connectedor coupled to the second load terminal Gnd. The source S of the firstswitching device T1 and the drain D of the second switching device T2may be electrically connected to each other and to an output terminalVph. The gate G of the first switching device T1 may be electricallycoupled or connected to a first control terminal Ctrl1 and the gate G ofthe second switching device T2 may be electrically coupled or connectedto a second control terminal Ctrl2. According to other embodiments, thegates G of the first and second switching devices T1, T2 may beelectrically connected to each other or at least one of the gates G maybe electrically connected to one of the load and output terminals Vdd,Gnd, Vph or to a driver circuit integrated in the integrated circuit500.

FIG. 1B refers to an embodiment of the integrated circuit 500 of FIG. 1Awith a lateral n-FET providing the first switching device T1 and avertical n-FET providing the second switching device T2. The integratedcircuit 500 is implemented on a semiconductor portion 100 of one or moresingle-crystalline semiconductor materials selected from a groupincluding silicon (Si), silicon carbide (SiC), germanium (Ge), a silicongermanium crystal (SiGe), gallium nitride (GaN) and gallium arsenide(GaAs), for example. The semiconductor portion 100 may have anessentially planar first surface 101 and a planar second surface 102parallel to the first surface 101 as main surfaces. A normal to thefirst surface 101 defines a vertical direction and directions orthogonalto the vertical direction are lateral directions.

The first switching device T1 includes a semiconductor region in a firstsection 100 a of the semiconductor portion 100. The second switchingdevice T2 includes a semiconductor region in a second section 100 b ofthe semiconductor portion 100. The first and second sections 100 a, 100b may be spaced from each other along the vertical direction, may forman interface parallel to the first and second surfaces 101, 102 or maypartly, but not totally, overlap each other. Electrode structures 310 b,311 a, 312 a, which are electrically connected to the first and secondswitching devices T1, T2, are arranged in the vertical projection of thesemiconductor portion 100.

The first switching device T1 may be a lateral n-FET of the enhancementtype including a plurality of approximately identical first transistorcells TC1, which may be regularly arranged at regular distances along atleast a first lateral direction. Each first transistor cell TC1 includesa first gate electrode 150 a arranged outside the semiconductor portion100 in a distance to the first surface 101 and a first gate dielectric205 a dielectrically insulating the first gate electrode 150 a from thefirst semiconductor region in the first section 100 a of thesemiconductor portion 100.

The first section 100 a the first semiconductor region of the firstswitching device T1 includes p-type first body zones 115 a, which may beportions of a p-type epitaxial layer, as well as heavily doped n-typefirst source zones 110 a and heavily doped n-type first drain zones 120a, which may extend as wells from the first surface 101 into the firstsubstrate section 100 a, respectively. A lightly doped n-type firstdrift zone 121 a may be provided between the first body zone 115 a andthe first drain zone 120 a of each first transistor cell TC1. Firstportions of the first body zones 115 a separate the first source anddrift zones 110 a, 121 a and adjoin the first surface 101. Secondportions of the first body zones 115 a separate the first source, drainand drift zones 110 a, 120 a, 121 a from the second switching device T2.

The first gate dielectrics 205 a dielectrically insulate the first gateelectrodes 150 a from the first portions of the first body zones 115 a.First cell insulators 202 a, which are thicker than the first gatedielectrics 205 a, may dielectrically insulate the first gate electrodes150 a from the first drift and drain zones 121 a, 120 a.

First contact structures 305 a extend between the first gate electrodes150 a into the semiconductor portion 100 and electrically connect thefirst source zones 110 a with a first source electrode 311 a and thefirst drain zones 130 a with a first drain electrode 312 a. The firstsource electrode 311 a may be electrically connected or coupled to anoutput terminal Vph and the first drain electrode 312 a may beelectrically connected or coupled to a first load terminal Vdd of theintegrated circuit 500. Dielectric spacers 220 a are provided betweenthe first contact structures 305 a and the first gate electrodes 150 aand a dielectric layer 222 a may dielectrically insulate the first gateelectrodes 150 a from the first source and drain electrodes 311 a, 312a.

The second switching device T2 may be a vertical n-FET of theenhancement type including a plurality of approximately identical secondtransistor cells TC2, which may be regularly arranged at equal distancesalong at least a first lateral direction. The vertical projections ofthe first and second semiconductor regions of the first and secondswitching devices T1, T2 overlap each other.

A center-to-center distance (pitch) between adjoining second transistorcells TC2 may be equal to, smaller than, or greater than the pitch ofadjoining first transistor cells TC1. The second transistor cells TC2are arranged in the vertical projection of at least some of the firsttransistor cells TC1, or vice versa.

Each second transistor cell TC2 includes a second gate electrode 150 bburied in the semiconductor portion 100 at a distance to the secondsurface 102 and a second gate dielectric 205 b dielectrically insulatingthe second gate electrode 150 b from the second semiconductor region inthe second section 100 b of the semiconductor portion 100.

The semiconductor region of the second switching device T2 may includeheavily doped n-type second source zones 110 b directly adjoining thesecond surface 102, a lightly doped n-type second drift zone 121 b,p-type second body zones 115 b spatially separating the second sourceand drift zones 110 b, 121 b and a second drain zone 120 b. Theinterfaces between the second body zones 115 b and the second driftzones 121 b as well as between the second drift and drain zones 121 b,120 b may be parallel to the first and second surfaces 101, 102.

The second gate electrodes 150 b are arranged in cell stripes extendingfrom the second surface 102 into the semiconductor portion 100. The cellstripes may further include field electrodes 160 b, wherein a fielddielectric 210 dielectrically insulates the field electrodes 160 b fromthe semiconductor material of the semiconductor portion 100 and thesecond gate electrodes 150 b. Second gate dielectrics 205 bdielectrically insulate the second gate electrodes 150 b from the secondbody zones 115 b.

A dielectric structure 220 b directly adjoins the second surface 102.Second contact structures 305 b extend through openings in thedielectric structure 220 b into the semiconductor portion 100. Thesecond contact structures 305 b may electrically connect the secondsource and body zones 110 b, 115 b with a second source electrode 310 b.The second source electrode 310 b may be electrically connected orcoupled to a second load terminal Gnd of the integrated circuit 500.Heavily doped p-type second contact zones 117 b may directly adjoin abottom portion of the second contact structures 305 b to provide a lowcontact resistance between the second contact structures 305 b and thesecond body zones 115 b.

Device connection structure 305 x may extend from the first surface 101into the semiconductor portion 100 and may electrically connect thesecond drain zone 120 b with the first source electrode 311 a. Alongsidewalls of the device connection structures 305 x heavily doped firstcontact zones 117 a may provide highly conductive connections betweenthe second source electrode 311 a and the first body zones 115 a.

The vertical projections of first and second transistor cells TC1, TC2overlap each other. The first transistor cells TC1 may be arranged inpairs, wherein the two transistor cells of each pair are arrangedmirror-inverted with regard to the first drain zone 120 a shared by theconcerned two first transistor cells TC1.

The embodiment of FIG. 1C differs from the embodiment of FIG. 1B in thatthe first source zones 110 a are patterned along a lateral directionperpendicular to the cross-sectional plane. In first sections, the firstsource zones 110 a extend from the first surface 101 to the second drainzone 120 b and provide an electrical connection between the first sourcezones 110 a of the first switching device T1 and the second drain zones120 b of the second switching device T2. In second sections, heavilydoped p-type first contact zones 117 a extend between the first sourcezones 110 a and the second drain zones 120 b and provide alow-resistivity connection between the adjoining first body zones 115 aand the first contact structures 305 a electrically connected to thefirst source electrode 311 a. Along the lateral direction perpendicularto the cross-sectional plane, the heavily doped p-type first contactzones 117 a alternate with sections of the heavily doped n-type firstsource zones 110 a. The second drain zone 120 b directly adjoinssections of the first source zones 110 a.

Alternatively, heavily doped p-type first contact zones 117 a separatethe first source zones 115 a from the second drain zone 120 b and thefirst contact structures 305 a extend into the second drain zone 120 bsuch that the first contact structures 305 a electrically connect thefirst source zones 110 a, the second drain zones 120 b, the first bodyzones 115 a and the first source electrode 311 a.

FIG. 1D is a schematic plan view of the electrode structures 311 a, 312a of the integrated circuit 500 at a side of the first surface 101. Thefirst source electrode 311 a may form an output terminal Vph, or aterminal pad for a bonding connection to the output terminal Vdd. Thefirst drain electrode 312 a may form a first load terminal Vdd or aterminal pad for a bonding connection to the first load terminal Vdd. Afirst control terminal Ctrl1 or terminal pad for a bonding connection tothe first control terminal Ctrl1 is electrically connected to the firstgate electrodes 150 a of FIGS. 1A-1C.

FIG. 1E shows the opposite side oriented to the second surface 102. Thesecond source electrode 310 b may form a second load terminal Vdd or aterminal pad for a bonding connection to the second load terminal Vdd. Asecond control terminal Ctrl2 or terminal pad for a bonding connectionto the second control terminal Ctrl2 is electrically connected to thesecond gate electrodes 150 b of FIGS. 1A-1C.

A further terminal or terminal pad may be electrically connected orcoupled to the second field electrodes 160 b. According to otherembodiments, the second field electrodes 160 b are electricallyconnected with the second source electrode 310 b or the second gateelectrodes 150 b. According to other embodiments, both control terminalsor terminal pads Ctrl1, Ctrl2 may be on the same side by providing a TSV(through-silicon via), for example.

The integrated circuit 500 may vertically integrate at least twoswitching devices T1, T2, e.g. the low side and high side switches of ahalf bridge. Low parasitic capacitance and electrical resistance betweenthe high side and low side switches and allows for a high packagingdensity. The integrated circuit 500 may be a power semiconductor device.

Compared to co-packaged dies with the high side and low side switchesprocessed in different dies obtained from different substrates andsoldered on top of each other or side-by-side, one way that theintegrated circuit 500 reduces packaging costs is that only one die mustbe handled and less package level interconnections are required.

Other than monolithic side-by-side implementations for half bridges, theintegrated circuit 500 allows for significantly reducing the requiredchip area.

FIGS. 2A to 2B refer to an integrated circuit 500 with a lateral p-FETproviding the first switching device T1 and a vertical n-FET providingthe second switching device T2. The second switching device T2 maycorrespond to the second switching device T2 of FIG. 1A. On the side ofthe first switching device T1, first contact structures 305 aelectrically connected to the first drain electrode 312 a and the firstload terminal Vdd directly adjoin the heavily doped p-type first drainzones 120 a as well as the n-type first body zones 115 a. First contactstructures 305 a electrically connected to the first source electrode311 a and the output terminal Vph directly adjoin the heavily dopedn-type second drain zone 120 b as well as the heavily doped p-type firstsource zones 110 a. For further details reference is made to thedescription of FIG. 1A to 1E.

FIGS. 3A to 3B refer to an embodiment that vertically integrates alateral HEMT as the first switching device T1 and a vertical n-FET asthe second switching device T2. The load paths of the first and secondswitching devices T1, T2 are electrically arranged in series. The firstand second switching devices T1, T2 may be configured in a cascodeconnection with the gate G of the first switching device T1 beingelectrically connected to the source S of the second switching deviceT2.

The second switching device T2 may correspond to the second switchingdevice T2 of FIG. 1A. The first switching device T1 may include at leasta buffer layer 180 and a barrier layer 182, both provided from Group IIInitrides or Group III arsenides, encompassing semiconductor compoundsformed from nitrogen or arsenic and Group III elements as gallium (Ga),aluminum (Al) and indium (In) and including ternary and tertiarycompounds like AlGaN and AlInGaN. The materials for the buffer andbarrier layers 180, 182 are selected from Group III nitrides/arsenidessuch that the band gaps of the materials for the barrier and bufferlayers 180, 182 differ significantly from each other and such that inproximity of the interface between the buffer and barrier layers 180,182 a two-dimensional electron gas (2DEG) provides a conductive channelin the buffer layer 180.

The conductive channel extends between a drain electrode provided by afirst contact structure 305 a electrically connected to the first loadterminal Vdd and a source electrode provided by a first contactstructure 305 a extending from the first surface 101 up to or into theheavily doped n-type second drain zone 120 b. A first gate electrode 150a, which may include a portion containing a conductive Group III nitrideor Group III arsenide material, may locally deplete or not deplete theconductive channel of the HEMT in response to a voltage applied to thefirst gate electrode 150 a.

The embodiment of FIGS. 4A and 4B combines two HEMTs as described aboveon opposing sides of a base substrate 400 shared by the two HEMTs. Thematerial of the base substrate 400 may be GaAs, SiC, Si, GaN, Ge, SiGe,or sapphire, for example. The first switching device T1 is a HEMTincluding first buffer and barrier layers 180 a, 182 a, wherein theexposed surface of the first barrier layer 182 a may form the firstsurface 101 of the semiconductor portion 100. The second switchingdevice T2 is a HEMT including second buffer and barrier layers 180 b,182 b, wherein the exposed surface of the second barrier layer 182 b mayform the second surface 107.

A device connection structure 305 x may extend from the first surface101 through the semiconductor portion 100 to the second surface 102,electrically connecting the first source electrode 311 a of the firstswitching device T1 and the second drain electrode 313 b of the secondswitching device T2.

According to other embodiments, a first portion of the device connectionstructure 305 x may extend from the first surface 101 into the basesubstrate 400 and a second portion may extend from the second surface102 into the base substrate 400. The first and second portions maydirectly adjoin each other. According to embodiments that include ahighly conductive base substrate 400, a portion of the base substrate400 may separate the first and second portions of the device connectionstructure 305 x.

FIGS. 5A to 5G relate to a method of manufacturing an integrated circuitvertically integrating a first switching device with first transistorcells and a second switching device with second transistor cells.

A base substrate 400 of a semiconductor substrate 500 a is provided fromone or more dielectric or semiconducting materials, e.g., sapphire,intrinsic or heavily doped single crystalline silicon (Si), singlecrystalline germanium (Ge), a silicon germanium crystal (SiGe), siliconcarbide (SiC), gallium nitride (GaN) or gallium arsenide (GaAs). Anauxiliary structure 140 may be provided on a first process surface 401of the base substrate 400.

FIG. 5A shows the auxiliary structure 140 formed on portions of thefirst process surface 401. The material of the auxiliary structure 140and the material of the base substrate 400 may have significantlydifferent etch properties. For example, the base substrate 400 isprovided from heavily doped n-type single-crystalline silicon and theauxiliary structure 140 is provided from a dielectric material, forexample a silicon oxide.

An epitaxy process grows an epitaxial layer 104 on the first surface 401and laterally overgrows the auxiliary structures 140 such that theepitaxial layer 104 and the base substrate 400 embed the auxiliarystructure 140. The materials of the base substrate 400 and the epitaxiallayer 104 may have identical or approximately identical latticeconstants such that the epitaxial layer 104 grows in registry with thecrystal lattice of the base substrate 400. The first epitaxial layer 104may consist of one homogeneously doped layer or may include two, threeor more sub-layers differing from each other as regards a verticalimpurity profile, a mean net impurity concentration and/or an impuritytype. The mean net dopant concentration, conductivity type and verticalimpurity profile of each sub-layer depends on the type of the switchingdevice(s) to be formed in the first epitaxial layer 104.

In FIG. 5B the first epitaxial layer 104 is a single-crystalline siliconlayer including a lightly doped p-type first sub-layer 104 a, a heavilydoped n-type second sub-layer 104 b and a lightly doped n-type thirdsub-layer 104 c. The exposed surface of the epitaxial layer 104 oppositeto the base substrate 400 may form a first surface 101 of asemiconductor portion of the finalized device.

Provisional or complete first transistor cells TC1 of a first switchingdevice T1 are formed in the first epitaxial layer 104 by deposition,implant and etch processes applied to the semiconductor substrate 500 afrom a side defined by the first surface 101. The first switching devicemay be a vertical switching device with first gate electrodes 150 a andfield electrodes 160 formed in cell stripes extending from the firstsurface 101 into the first epitaxial layer 104. First gate dielectrics205 a dielectrically insulate the first gate electrodes 150 a from thefirst epitaxial layer 104. Field dielectrics 202 may dielectricallyinsulate the field electrodes 160 from the epitaxial layer 104 and thefirst gate electrodes 150 a.

A first dielectric structure 220 a may be provided on the first surface101 and contact grooves 105 may be etched through openings in the firstdielectric structure 220 a into semiconductor mesas formed betweenadjoining cell stripes. Additional impurities may be introduced into thefirst epitaxial layer 104 by diffusion and/or implant processes throughthe first surface 101 for forming source zones, channel/body zones andcontact zones. In the case of implants, the implant damages may or maynot be annealed at this stage and the implants may or may not bediffused at this stage. A thin metal barrier liner 301 may be depositedthat lines the contact grooves 105 and that covers the first dielectricstructure 220 a.

FIG. 5C shows the completed or provisional first transistor cells TC1and the metal barrier liner 301. The metal barrier liner 301 may consistof or contain titanium nitride (TiN) or tantalum nitride (TaN), by wayof example. The second sub-layer 104 b may correspond to or include afirst drain zone 120 a and the third sub-layer 104 c may correspond toor include a first drift zone 121 a of the first switching device.

A protection layer 710 may be deposited on the metal barrier liner 301and a carrier 720 may be fixed, e.g. adhered or bonded, to theprotection layer 710.

FIG. 5D shows the protection layer 710 provided from a material that canbe removed with high selectivity against the material of the metalbarrier liner 301 and withstands the process temperatures applied forproviding the second switching device, e.g. a glass. The carrier 720 maybe a metal chunk or a silicon plate directly bonded to asilicon-containing protection layer 710, by way of example.

The semiconductor substrate 500 a is turned upside down (flipped) suchthat a second process surface of the base substrate 400 side opposite tothe first surface 101 is accessible for deposition, etch, implant andpolishing processes. The base substrate 400 may be thinned or may beremoved completely, e.g. by a chemical/mechanical polishing process. Inaddition to the base substrate 400, other embodiments may provideremoving a portion of the first epitaxial layer 104 adjoining the basesubstrate 400. The auxiliary structures 140 may be used for endpointdetection in a polishing process.

FIG. 5E shows the semiconductor substrate 500 a after a polishingprocess completely removes the base substrate 400 and stops at theauxiliary structures 140. The polished surface of the epitaxial layer140 may form the second surface 102 of the semiconductor portion 100 ofthe finalized device. Defects in a portion of the first epitaxial layer104 oriented to the second surface 102 may be cured, for example byusing etching, annealing, and/or oxidation processes and generating asacrificial oxide, which may be removed in the following. A furtherepitaxial layer may or may not be grown on the surface of thesemiconductor substrate 500 a opposite to the first surface 101.

Second complete or provisional transistor cells TC2 of the secondswitching device may be formed by providing second gate electrodes 150b, second gate dielectrics 205 b that dielectrically insulate the secondgate electrodes 150 b from the semiconductor portion 100, and a seconddielectric structure 220 b dielectrically encapsulating the second gateelectrodes 150 b. The second switching device may be an LDMOS-FET(laterally diffused metal oxide semiconductor FET) in the usual meaningincluding both metal gate electrodes and non-metal gate electrodes.Additional impurities may be introduced into the first sub-layer 104 aby diffusion and/or implant processes through the second surface 102 forforming channel or body, drain, source and contact zones. In the case ofimplants, the implant damages may or may not be annealed at this stageand the implants may or may not be diffused at this stage.

FIG. 5F shows the second completed or provisional transistor cells TC2with second gate dielectrics 205 b dielectrically insulating the secondgate electrodes 150 b from the first epitaxial layer 104.

An etch process may remove the auxiliary structures 140 with highselectivity against the material of the first epitaxial layer 104 toform device connection grooves extending from the second surface 102into the semiconductor portion 100. The etch process may expose theheavily doped second sub-layer 104 b and a further etch process, whichmay remove heavily doped material at a higher rate than lightly dopedmaterial, may be used to deepen the device connection grooves. Deviceconnection structures 305 x may be formed in the device connectiongrooves.

FIG. 5G shows second transistor cells TC2 of the switching device T2 anddevice connection structures 305 x in place of the auxiliary structures140 of FIG. 5A. The device connection structures 305 x may extend intothe second sub-layer 104 b and may electrically connect the first drainzones 120 a of the first switching device T1 with second source zones ofthe second switching device T2.

After providing the electrodes of the second switching device T2, thecarrier 720 and the protection layer 710 are removed and the electrodestructures of the first switching device T1 may be completed. Thefinalized device may in substance correspond to the integrated circuit500 of FIG. 1B.

Annealing and/or diffusion of implants concerning the first and secondswitching devices T1, T2 may be carried out separately or may becombined with each other, e.g. the annealing or the diffusion processesmay be carried out simultaneously. Other embodiments may flip thesemiconductor substrate 500 a before or after forming the metal barrierliner 301 or may flip the semiconductor substrate 500 a more than once.

FIGS. 6A to 6E refer to the manufacture of an integrated circuit thatvertically integrates two HEMTs. On a first process surface 401 of abase substrate 400, for example on a (111)-surface of a silicon crystal,an epitaxy process grows a first epitaxial layer including at least twogroup III nitride layers with different band gaps, for example a firstbuffer layer 180 a and a first barrier layer 182 a.

FIG. 6A shows the first buffer layer 180 a, e.g. a GaN layer, on thefirst process surface 401 and the first barrier layer 182 a, e.g. anAlGaN or InAlN layer, on the first buffer layer 180 a. An exposedsurface of the first barrier layer 182 a opposite to the base substrate400 may correspond to the first surface 101 of a semiconductor portionof the finalized device. Other embodiments may provide a seed layer froma further group III nitride between the base substrate 400 and the firstbuffer layer 180 a.

First source and drain contacts 305 a and a first gate electrode 150 aare formed in and on the first epitaxial layer and a passivation layer190 may be deposited.

As shown in FIG. 6B, the first source and drain contacts 305 a extendfrom the first surface 101 through the first barrier layer 182 a intothe first buffer layer 180 a. The first gate electrode 150 a is providedat a distance to an interface between the first buffer and barrierlayers 180 a, 182 a. The passivation layer 190 covers the first surface101 and encapsulates the first gate electrode 150 a as well as the firstsource and drain contacts 305 a. One of the drain and source contacts305 a, for example the drain contact 305 a, may extend through the firstbuffer layer 180 a and may directly adjoin the base substrate 400 toprovide a portion of a device connection structure.

The semiconductor substrate 500 a is turned upside down such that asecond process surface 402 of the base substrate 400 side opposite tothe first surface 101 is accessible for deposition, etch, implant andpolishing processes. The base substrate 400 may or may not be thinned ina grinding process.

FIG. 6C shows the flipped semiconductor substrate 500 a with the thinnedbase substrate 400 a providing a further process surface 403 opposite tothe passivation layer 190.

A second epitaxial layer selected from group III nitrides is grown onthe further process surface 403. The second epitaxial layer includes atleast a second buffer layer 180 b and a second barrier layer 182 b.

In FIG. 6D the second buffer layer 180 b directly adjoins the thinnedbase substrate 400 a opposite to the first buffer layer 180 a. Anexposed surface of the second barrier layer 182 b provides the secondsurface 102 of the semiconductor portion 100 of the finalized device.The materials and dimensions of the first and second buffer layers 180a, 180 b may be the same or may be different.

Second gate electrodes 150 b as well as second source and drain contacts305 b are formed on and in the second epitaxial layer similar to thefirst gate electrodes 150 a and first source and drain contacts 305 a.One of the second drain and source contacts 305 b, for example thesecond source contact 305 a, may extend through the second buffer layer180 b, and may directly adjoin the base substrate 400.

In FIG. 6E, the extended first drain and second source contacts 305 a,305 b may directly adjoin each other and may form portions of acontiguous device connection structure 305 x, wherein the thinned basesubstrate 400 a may be based on a conductive or a dielectric material.

According to other embodiments, the extended first drain and secondsource contacts 305 a, 305 b do not directly adjoin each other, whereinthe thinned base substrate 400 a is based on a conductive material andis part of the device connection structure.

An embodiment of an integrated circuit includes a first switching deviceincluding a first semiconductor region in a first section of asemiconductor portion and a second switching device including a secondsemiconductor region in a second section of the semiconductor portion.The first and second sections and electrode structures of the first andsecond switching devices outside the semiconductor portion are arrangedalong a vertical axis perpendicular to a first surface of thesemiconductor portion. The first and second sections of thesemiconductor portion may directly adjoin each other and form aninterface parallel to the first surface.

Another embodiment of an integrated circuit includes a first switchingdevice including a first semiconductor region in a first section of asemiconductor portion and a second switching device including a secondsemiconductor region in a second section of the semiconductor portion.The first and second sections and electrode structures of the first andsecond switching devices outside the semiconductor portion are arrangedalong a vertical axis perpendicular to a first surface of thesemiconductor portion. A device connection structure electricallyconnects one of the electrode structures of the first switching devicewith one of the electrode structures of the second switching device. Thedevice connection structure is arranged between the first surface and anopposite second surface of the semiconductor portion and is embedded inthe semiconductor portion.

Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat a vatiety of alternate and/or equivalent implementations may besubstituted for the specific embodiments shown and described withoutdeparting from the scope of the present invention. This application isintended to cover any adaptations or variations of the specificembodiments discussed herein. Therefore, it is intended that thisinvention be limited only by the claims and the equivalents thereof.

What is claimed is:
 1. A method of manufacturing an integrated circuit,the method comprising: growing an epitaxial layer on a process surfaceof a base substrate; forming, by processes applied to an exposed firstsurface of the epitaxial layer, first transistor cells in the epitaxiallayer, each first transistor cell comprising a first gate electrode; andforming, by processes applied to a surface opposite to the firstsurface, second transistor cells, each second transistor cell comprisinga second gate electrode.
 2. The method of claim 1, further comprising:removing at least a portion of the base substrate after forming thefirst transistor cells and before forming the second transistor cells.3. The method of claim 1, wherein the second transistor cells are formedin the epitaxial layer.
 4. The method of claim 1, wherein the secondtransistor cells are formed in the base substrate.
 5. The method ofclaim 1, further comprising: growing, after forming the first transistorcells, a further epitaxial layer on a side of the base substrateopposite to the epitaxial layer with the first transistor cells, whereinthe second transistor cells are formed in the further epitaxial layer.6. The method of claim 1, further comprising: forming, before growingthe epitaxial layer, an auxiliary structure from a material differentfrom a material of the base substrate on the process surface.
 7. Themethod of claim 6, further comprising: removing, before forming thesecond transistor cells, the base substrate after forming the firsttransistor cells, wherein the auxiliary structure and a second surfaceare exposed.
 8. The method of claim 7, wherein forming the secondtransistor cells comprises forming the second gate electrodes of thesecond transistor cells on the second surface.
 9. The method of claim 8,further comprising: removing, before forming the second transistorcells, the auxiliary structure selectively against the epitaxial layerso as to form a device connection groove.
 10. The method of claim 9,further comprising: forming a device connection structure in the deviceconnection groove.
 11. The method of claim 10, wherein the firsttransistor cells are vertical transistor cells, forming the firsttransistor cells comprises forming a common drain zone of the firsttransistor cells in the epitaxial layer, and wherein the deviceconnection structure directly adjoins the common drain zone.
 12. Themethod of claim 6, wherein the auxiliary structure is formed from adielectric material.
 13. The method of claim 1, wherein forming theepitaxial layer comprises forming at least two group III nitride layers.14. The method of claim 13, wherein forming the first transistor cellscomprises forming a first source contact and a first drain contactextending from a first surface of the epitaxial layer into the epitaxiallayer, wherein one of the first source contact and the first draincontact extends into the base substrate.
 15. The method of claim 14,wherein forming the first transistor cells further comprises forming afirst gate electrode on the first surface of the epitaxial layer. 16.The method of claim 14, further comprising: growing, after forming thefirst transistor cells, a further epitaxial layer on a side of the basesubstrate opposite to the epitaxial layer with the first transistorcells, wherein the second transistor cells are formed in the furtherepitaxial layer.
 17. The method of claim 16, wherein forming the secondtransistor cells comprises forming a second source contact and a seconddrain contact extending from a second surface of the further epitaxiallayer into the epitaxial layer, wherein one of the second drain contactand the second source contact extends into the base substrate.
 18. Themethod of claim 17, wherein the base substrate is conductive.
 19. Themethod of claim 17, wherein either the first drain contact and thesecond source contact or the second drain contact and the first sourcecontact directly adjoin to each other and form a continuous deviceconnection structure extending from the first surface to the secondsurface.